VHDL for logic synthesis (Record no. 74964)
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000 -LEADER | |
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fixed length control field | 00703 2200205 4500 |
005 - DATE AND TIME OF LATEST TRANSACTION | |
control field | 20121022115527.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 121022t xxu||||| |||| 00| 0 eng d |
080 ## - UNIVERSAL DECIMAL CLASSIFICATION NUMBER | |
Universal Decimal Classification number | 621.3.049.77 |
Item number | RUS |
100 ## - MAIN ENTRY--PERSONAL NAME | |
Personal name | Rushton, Andrew |
245 ## - TITLE STATEMENT | |
Title | VHDL for logic synthesis |
300 ## - PHYSICAL DESCRIPTION | |
Extent | xvi, 466 p. |
653 ## - INDEX TERM--UNCONTROLLED | |
Uncontrolled term | Computer hardware description language-VHDL |
653 ## - INDEX TERM--UNCONTROLLED | |
Uncontrolled term | Logic design-Data processing |
653 ## - INDEX TERM--UNCONTROLLED | |
Uncontrolled term | Computer aided design |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
item type | Books |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
Name of publisher, distributor, etc | John Wiley & Sons |
Date of publication, distribution, etc | 2011 |
Place of publication, distribution, etc | Sussex |
250 ## - EDITION STATEMENT | |
Edition statement | 3rd ed. |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
International Standard Book Number | 9780470688472 |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
-- | 20650 |
Lost status | Source of classification or shelving scheme | Not for loan | Home library | Current library | Shelving location | Date acquired | Cost, normal purchase price | Total Checkouts | Full call number | Barcode | Date last seen | Date checked out | Cost, replacement price | Price effective from | Koha item type |
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Universal Decimal Classification | University Library | University Library | General Stacks | 01/03/2012 | 0.00 | 7 | 621.3.049.77 RUS | 00067620 | 24/10/2019 | 22/09/2019 | 0.00 | 01/03/2012 | Books |