| 000 | 00703 a2200205 4500 | ||
|---|---|---|---|
| 005 | 20121022115527.0 | ||
| 008 | 121022t xxu||||| |||| 00| 0 eng d | ||
| 080 |
_a621.3.049.77 _bRUS |
||
| 100 |
_aRushton, Andrew _922011 |
||
| 245 | _aVHDL for logic synthesis | ||
| 300 | _axvi, 466 p. | ||
| 653 | _aComputer hardware description language-VHDL | ||
| 653 | _aLogic design-Data processing | ||
| 653 | _aComputer aided design | ||
| 942 | _cBK | ||
| 260 |
_bJohn Wiley & Sons _c2011 _aSussex _920650 |
||
| 250 | _a3rd ed. | ||
| 020 | _a9780470688472 | ||
| 952 |
_w2012-03-01 _p00067620 _v0.00 _r2012-03-01 _40 _e94 _00 _bUL _10 _o621.3.049.77 RUS _d2012-03-01 _70 _cGEN _2udc _g0.00 _yBK _aUL |
||
| 999 |
_c74964 _d74963 |
||